1. Field of Use
The present disclosure relates generally to electronic circuits, and more specifically, to a comparator.
2. Related Art
A type of comparator for use in, for instance, an analog-to-digital converter (ADC) or the like includes a comparator circuit and a latch circuit for outputting a digital signal in sequence with a clock signal. FIG. 1 provides an example of a comparator 100. In FIG. 1, the comparator 100 includes a supply voltage source node 101, a supply voltage source node 102, a constant current source circuit 110, a bias circuit 120, a comparator circuit 130, a current mirror circuit 140, a latch circuit 150, and a set-reset (SR) flip-flop circuit 160. Further, the comparator 100 includes an input node 103 and a reference node 105. In addition, the comparator 100 includes output nodes 107 and 108.
In FIG. 1, the constant current source circuit 110 provides a constant bias current to the bias circuit 120. The bias circuit 120 mirrors the constant bias current in providing a continuous, uninterrupted bias current to the comparator circuit 130, which places the comparator circuit 130 in an active mode. In this example, the comparator circuit 130 is a differential amplifier. The comparator circuit 130 compares an input signal at the input node 103 with a reference signal at the reference node 105 to provide a difference signal and an inverted difference signal. The current mirror circuit 140 operates by mirroring the difference signal and the inverted difference signal to the output nodes 107 and 108, respectively. The latch circuit 150 is used to latch the voltage levels at the output nodes 107 and 108 to generate a first and second latched signals. The latched signals are then stored by the SR flip-flop circuit 160.
In operation, if the clock signal is low at the gate node of the transistor 153, then the transistor 153 is in an inactive mode. Therefore, the latch circuit 150 is operated in a regenerate state. Thus, the latch circuit 150 latches the difference signal at the output node 107 and the inverted difference signal at the output node 108 to the voltage level at either the voltage supply source node 101 or the voltage supply source node 102. The held voltage levels on each of the output nodes 107 and 108 are input to and stored by the SR flip-flop circuit 160, For instance, if the voltage level of the signal at the input node 103 is greater than the voltage level of the signal at the reference node 105, then the latch circuit 150 during regenerate state will latch the voltage level on the output node 107 to the voltage supply source node 102 and will latch the voltage level on the output node 108 to the voltage supply source node 101. Thus, the SR flip-flop circuit 160 will store a high voltage level.
Similarly, if the voltage level of the signal at the input node 103 is less than the voltage level of the signal at the reference node 105, then the latch circuit 150 during regenerate state will latch the voltage level on the output node 107 to the voltage supply source node 101 and will hold the voltage level on the output node 108 to the voltage supply source node 102. Thus, the SR flip-flop circuit 160 will store a low voltage level. If the clock signal at the gate of the transistor 153 is at its high voltage level, then the transistor 153 is in an active mode. Therefore, the latch circuit 150 is in a reset state. Thus, the voltage level at each of the output nodes 107 and 108 rapidly approach the same voltage level.
FIG. 2 shows waveforms 200 useful for understanding the relationship between a clock signal 201, an output signal 211, an instantaneous current 221, and a bias current 231 in the comparator 100 shown in FIG. 1. The graphical illustration in its entirety is referred to by 200. In operation, when the clock signal 201 is at a high voltage level, the latch circuit 150 is in its reset state. During the reset state, the voltage levels on the output nodes 107 and 108, as referenced by 212 and 213, respectively, equalize to about the same voltage level, as referenced by 214, Similarly, when the clock signal 201 is at a low voltage level, the latch circuit 150 is in its regenerate state. During the regenerate state, the voltage levels on the output nodes 107 and 108 latch at either the voltage level on the voltage supply source node 101 or the voltage level on the voltage supply source node 102, as referenced by 215 and 216, respectively. The instantaneous current 221 is appreciable at the start of the regenerate state, However, the bias current 231 is appreciable, continuous, and substantially constant throughout the operation of the comparator 100. Therefore, the bias current 231 is a significant portion of the overall current consumed by the comparator 100.